Field-programmable gate arrays (FPGAs) are widely used for low- and medium-volume chips, but they have failed dominate over the high-volume market, because of their high cost which results from a large silicon area of the device. The most common FPGA architecture consists of an array of logic blocks (LBs), I/O pads, and routing channels. In the LB, look-up table (LUT) is used as a “soft” function generator to realize various functions, which leads to very high functionality but causes large area of the device. It has been shown that a simple look-up table (LUT)/flip-flop (FF) FPGA requires about 35 times the area of a cell-based application-specific integrated circuit (ASIC). To narrow this gap, frequently used dedicated “hard” circuits such as carry chains, adders and multipliers have been employed in FPGA design as shown in the non-patent document 1.
The “soft” LUT is conventionally constructed by a multiplexer (MUX), while a “hard” circuit can also be constructed by a MUX if pass transistor logic (PTL) is used. The “hard” circuits are very efficient when they are used. Otherwise, they are wasted. To overcome the negative impact of the “hard” circuit, concept of sharing common MUX to implement “soft” and “hard” circuits has been introduced in the non-patent document 2.
As shown in FIG. 1A, a 2n:1 MUX 101 is shared to construct a reconfigurable circuit to implement a LUT and a “hard” circuit. A MUX input switch block 102 selects either a memory value or a data input (or its inverse) as the input of the MUX 101 for a LUT mode or a “hard” circuit mode. The MUX input switch block 102 is composed of a memory ms and nMOS pass transistors Tr in conventional CMOS technology as shown in patent document 1. The nMOS transistors Tr are connected to the two-state memories m1, . . . , m2n as shown in FIG. 1B. When the ms is configured as “1”, memories m1, . . . , m2n are connected with the 2n:1 MUX 101's input ports V1, . . . , V2n, so that n-input LUT can be implemented. When the ms is configured as “0”, data input D and its inverse ˜D are applied to the 2n:1 MUX 101's input ports V1, . . . , V2n, so that a “hard circuit” can be implemented. The 2n:1 MUX 101 can be efficiently utilized. However, the MUX input switch block 102 causes large area of the device.
As a basic “hard” circuit, a full adder (FA) is used to construct multi-bit adder and multiplier in conventional FPGAs. As shown in FIG. 2A, an 8:1 MUX 201 is shared to implement a 3-input LUT and the FA, which leads to high utilization of the hardware resources. The 8:1 MUX 201 has one output and two intermediate outputs, wherein signals A and B select one input from among inputs V1, . . . , V4 as the intermediate OUTIM1, signals A and B select one input from among inputs V5, . . . , V8 as the intermediate OUTIM2, signal M select one of OUTIM1 and OUTIM2 as a final output OUT. When the ms is configured as “1”, memories m1, . . . , m8 are connected with the 8:1 MUX 201's input ports V1, . . . , V8, so that 3-input LUT can be implemented. When the ms is configured as “0”, carry input Cin and its inverse ˜Cin are applied to the 8:1 MUX 201's input ports V1, . . . , V8, so that the FA can be implemented according to the truth table shown in FIG. 2B. The MUX input switch block 202 is composed of 12 nMOS transistors Tr and a memory Ms constructed by 6 transistors (if a conventional SRAM is used), which results in large area of the device.    Non-patent document 1: P. A. Jamieson and J. Rose, “Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, pp. 1696-1709, December 2010.    Non-patent document 2: X. BAI, M. KAMEYAMA, Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI, IEICE TRANSACTIONS on Electronics, Vol. E97-C, No. 10, pp. 1028-1035    Non-patent document 3: Shunichi Kaeriyama et al., A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch, IEEE Journal of Solid-State Circuits, January 2005, pp. 168-176, vol. 40, No. 1.    Patent document 1: U.S. Pat. No. 7,019,557    Patent document 2: U.S. Pat. No. 8,816,312